Validate any dependencies needed to fuse the two insns together. Two SET insns or a compare and a conditional jump and this hook should Group, and they will not be scheduled apart. ( prev and curr), the scheduler will put them into a sched If this hook returns true for the given insn pair This hook is used to check whether two insns should be macro fused forĪ target microarchitecture. Target Hook: bool TARGET_SCHED_MACRO_FUSION_PAIR_P (rtx_insn * prev, rtx_insn * curr) ¶ This hook is used to check whether target platform supports macro fusion. Target Hook: bool TARGET_SCHED_MACRO_FUSION_P (void) ¶ These other insns can then be taken into account properly. Scheduling one insn causes other insns to become ready in the sameĬycle. This hook can be useful if there are frequent situations where Return the number of insns to be scheduled in the same cycle. ‘ TARGET_SCHED_VARIABLE_ISSUE’ it can reorder the ready list and Is called once per iteration over a cycle, immediately after Thatįunction is called whenever the scheduler starts a new cycle. Like ‘ TARGET_SCHED_REORDER’, but called at a different time. Target Hook: int TARGET_SCHED_REORDER2 (FILE * file, int verbose, rtx_insn ** ready, int * n_readyp, int clock) ¶ The return value is the number of insns thatĬan issue this cycle normally this is just issue_rate. Reads the ready list in reverse order, starting with n_readyp isĪ pointer to the number of elements in the ready list. List of instructions that are ready to be scheduled. List, to allow the machine description to reorder it (for example toĬombine two small instructions together on ‘ VLIW’ machines). This hook is executed by the scheduler after it has scheduled the ready Target Hook: int TARGET_SCHED_REORDER (FILE * file, int verbose, rtx_insn ** ready, int * n_readyp, int clock) ¶ Do not define this hook if you do not need to adjust the Increase the priority toĮxecute insn earlier, reduce the priority to execute insn This hook adjusts the integer scheduling priority priority of Target Hook: int TARGET_SCHED_ADJUST_PRIORITY (rtx_insn * insn, int priority) ¶ See Specifying processor pipeline description. If these values are notĪcceptable, you could use the hook to modify them too. Output-dependence is maximum of one and the difference of latency If the scheduler using the automaton based pipelineĭescription, the cost of anti-dependence is zero and the cost of Used for example to specify to the scheduler using the traditional pipelineĭescription that an output- or anti-dependence does not incur the same costĪs a data-dependence. The default is to make no adjustment to cost. Relationship between insn and dep_insn through aĭependence of type dep_type, and strength dw. This function corrects the value of cost based on the Target Hook: int TARGET_SCHED_ADJUST_COST (rtx_insn * insn, int dep_type1, rtx_insn * dep_insn, int cost, unsigned int dw) ¶ Than others, so that fewer insns can follow them in the same cycle.įile is either a null pointer, or a stdio stream to write anyĭebug output to. You should define this hook if some insns take more machine resources USE, which normally are not counted against the issue rate. ‘ more - 1’ for insns other than CLOBBER and It should return the number of insns which can This hook is executed by the scheduler after it has scheduled an insnįrom the ready list. Target Hook: int TARGET_SCHED_VARIABLE_ISSUE (FILE * file, int verbose, rtx_insn * insn, int more) ¶ It to vary depending on what the instructions are, you must use This value must be constant over the entire compilation. Hooks ‘ TARGET_SCHED_REORDER’ and ‘ TARGET_SCHED_REORDER2’).
The default is one.Īlthough the insn scheduler can define itself the possibility of issueĪn insn on the same cycle, the value can serve as an additionalĬonstraint to issue insns on the same simulated processor cycle (see Issue at the same time on the target machine. This hook returns the maximum number of instructions that can ever Target Hook: int TARGET_SCHED_ISSUE_RATE (void) ¶ Them: try the first ones in this list first. It is usually enough to define just a few of The instruction scheduler may need a fair amount of machine-specificĪdjustment in order to produce good code.
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